Latch Transparent 3-ST 8-CH D-Type 20-Pin CDIP
| 유럽 연합 RoHS 명령어 | Not Compliant |
| 미국수출통제분류ECCN 인코딩 | 3A001.a.2.c |
| 친환경 무연 | Active |
| 미국 세관 상품 코드 | 8542.39.00.60 |
| SVHC | Yes |
| Automotive | No |
| PPAP | No |
| Type | D-Type |
| Logic Family | ACTQ |
| Latch Mode | Transparent |
| Number of Channels per Chip | 8 |
| Number of Elements per Chip | 1 |
| Number of Inputs per Chip | 8 |
| Number of Input Enables per Element | 1 |
| Number of Selection Inputs per Element | 0 |
| Number of Outputs per Chip | 8 |
| Number of Output Enables per Element | 1 |
| Bus Hold | No |
| Set/Reset | No |
| Polarity | Non-Inverting |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 10.5@5V |
| Absolute Propagation Delay Time (ns) | 11.5 |
| Process Technology | CMOS |
| Output Type | 3-State |
| Maximum Low Level Output Current (mA) | 24 |
| Maximum High Level Output Current (mA) | -24 |
| Minimum Operating Supply Voltage (V) | 4.5 |
| Typical Operating Supply Voltage (V) | 5 |
| Maximum Operating Supply Voltage (V) | 5.5 |
| Maximum Quiescent Current (uA) | 80 |
| Propagation Delay Test Condition (pF) | 50 |
| Minimum Operating Temperature (°C) | -55 |
| Maximum Operating Temperature (°C) | 125 |
| Supplier Temperature Grade | Military |
| Mounting | Through Hole |
| Package Height | 4.57(Max) |
| Package Width | 7.87(Max) |
| Package Length | 25.02(Max) |
| PCB changed | 20 |
| Standard Package Name | DIP |
| Supplier Package | CDIP |
| Pin Count | 20 |
| Lead Shape | Through Hole |
| EDA / CAD Models |
|
A datasheet is only available for this product at this time.
문의 및 지원
프로그램 및 파트너
주요 제품
제품 카테고리
제조업체
Latch Transparent 3-ST 8-CH D-Type 20-Pin CDIP
| 유럽 연합 RoHS 명령어 | Not Compliant |
| 미국수출통제분류ECCN 인코딩 | 3A001.a.2.c |
| 친환경 무연 | Active |
| 미국 세관 상품 코드 | 8542.39.00.60 |
| SVHC | Yes |
| Automotive | No |
| PPAP | No |
| Type | D-Type |
| Logic Family | ACTQ |
| Latch Mode | Transparent |
| Number of Channels per Chip | 8 |
| Number of Elements per Chip | 1 |
| Number of Inputs per Chip | 8 |
| Number of Input Enables per Element | 1 |
| Number of Selection Inputs per Element | 0 |
| Number of Outputs per Chip | 8 |
| Number of Output Enables per Element | 1 |
| Bus Hold | No |
| Set/Reset | No |
| Polarity | Non-Inverting |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 10.5@5V |
| Absolute Propagation Delay Time (ns) | 11.5 |
| Process Technology | CMOS |
| Output Type | 3-State |
| Maximum Low Level Output Current (mA) | 24 |
| Maximum High Level Output Current (mA) | -24 |
| Minimum Operating Supply Voltage (V) | 4.5 |
| Typical Operating Supply Voltage (V) | 5 |
| Maximum Operating Supply Voltage (V) | 5.5 |
| Maximum Quiescent Current (uA) | 80 |
| Propagation Delay Test Condition (pF) | 50 |
| Minimum Operating Temperature (°C) | -55 |
| Maximum Operating Temperature (°C) | 125 |
| Supplier Temperature Grade | Military |
| Mounting | Through Hole |
| Package Height | 4.57(Max) |
| Package Width | 7.87(Max) |
| Package Length | 25.02(Max) |
| PCB changed | 20 |
| Standard Package Name | DIP |
| Supplier Package | CDIP |
| Pin Count | 20 |
| Lead Shape | Through Hole |
| EDA / CAD Models |
A datasheet is only available for this product at this time.
제조업체
