Texas InstrumentsCDCLVP1216EVM
CDCLVP1216 Clock Buffer and Driver Evaluation Board
| RoHS Not Applicable | |
| EAR99 | |
| Active | |
| 8473.30.11.80 | |
| SVHC | Yes |
| SVHC 기준 초과 | Yes |
| Automotive | No |
| PPAP | No |
| Evaluation Board | |
| CDCLVP1216 | |
| Clock Buffer and Driver | |
| 3.6(Max) |
Dev Kit Description
CDCLVP1216EVM is the evaluation module for CDCLVP1216. The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs. It has a maximum clock frequency up to 2 GHz. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 30 ps, making the device a perfect choice for use in demanding applications.
Dev Kit Features
-2:16 LVPECL Differential Buffer
-Selectable Clock Inputs Through Control Pin
-Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL
-Maximum Clock Frequency: 2 GHz
-Maximum Core Current Consumption: 110mA
-Very Low Additive Jitter: < 100 fs,rms in 10 kHz to 20 MHz Offset Range
-2.375 V to 3.6 V Device Power Supply
-Maximum Propagation Delay: 550 ps
-Maximum Output Skew: 30 ps
-Industrial Temperature Range: -40°C to +85°C
-ESD Protection Exceeds 2 kV (HBM
-Available in 7-mm X 7-mm QFN-48 (RGZ) PackageKit Includes
-SCAU029, CDCLVP1216EVM User's Guide
-SCAS877, 16 LVPECL Output High-Performance Clock Buffer (Rev. C)Dev Kit Additional Information
http://www.ti.com/lit/ds/symlink/cdclvp1216.pdf
| EDA / CAD Models |