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Lattice SemiconductorDDR2CTWB-M2-UIP Cores
DDR2 SDRAM Controller - Pipelined
| Compliant | |
| EAR99 | |
| Active | |
| EA | |
| Automotive | No |
| PPAP | No |
| Memory Controller | |
| MachXO2 |
| EDA / CAD Models |
DDR2 SDRAM Controller - Pipelined
| Compliant | |
| EAR99 | |
| Active | |
| EA | |
| Automotive | No |
| PPAP | No |
| Memory Controller | |
| MachXO2 |
| EDA / CAD Models |