| 欧盟RoHS指令 | Compliant |
| 美国出口管制分类ECCN编码 | 3A991 |
| 环保无铅 | NRND |
| 美国海关商品代码 | 8542.31.00.60 |
| SVHC | Yes |
| Automotive | No |
| PPAP | No |
| Family Name | Stratix® V GX |
| User I/Os | 552 |
| Process Technology | 28nm |
| Number of Registers | 740000 |
| Shift Registers | Utilize Memory |
| Operating Supply Voltage (V) | 0.85 |
| Logic Elements | 490000 |
| Number of Multipliers | 512 (18x18) |
| Program Memory Type | SRAM |
| Embedded Memory (Kbit) | 46080 |
| Total Number of Block RAM | 2304 |
| EMACs | 2 |
| IP Core | RapidIO to AXI Bridge Controller (RAB)|RLDRAM II Controller Core|SPAUI MAC|Sub-frame Latency JPEG 2000 Encoder (BA130)|Viterbi Compiler, Low-Speed/Hybrid Serial Decoder |
| Provider Name | Altera/Barco Silex/Mobiveil, Inc/Commsonic |
| Device Logic Units | 490000 |
| Number of Global Clocks | 16 |
| Device Number of DLLs/PLLs | 28 |
| Transceiver Channels | 48 |
| Transceiver Speed (Gbps) | 14.1 |
| Dedicated DSP | 256 |
| PCIe | 4 |
| Programmability | Yes |
| Reprogrammability Support | Yes |
| Copy Protection | No |
| In-System Programmability | Yes |
| Speed Grade | 2 |
| Differential I/O Standards | HCSL|LVDS|LVPECL |
| Single-Ended I/O Standards | LVCMOS|LVTTL |
| External Memory Interface | DDR2 SDRAM|DDR3 SDRAM|QDRII+SRAM|RLDRAM II|RLDRAM III |
| Minimum Operating Supply Voltage (V) | 0.82 |
| Maximum Operating Supply Voltage (V) | 0.88 |
| I/O Voltage (V) | 1.2|1.25|1.35|1.5|1.8|2.5|3 |
| Minimum Operating Temperature (°C) | 0 |
| Maximum Operating Temperature (°C) | 85 |
| Supplier Temperature Grade | Commercial |
| Packaging | Tray |
| Tradename | Stratix |
| Mounting | Surface Mount |
| Package Height | 2.83 |
| Package Width | 35 |
| Package Length | 35 |
| PCB changed | 1152 |
| Standard Package Name | BGA |
| Supplier Package | FBGA |
| Pin Count | 1152 |
