| 欧州RoHS | Compliant |
| ECCN (US) | 3A991a.2. |
| Part Status | Active |
| HTS | 8542.31.00.15 |
| Automotive | Yes |
| PPAP | No |
| Family Name | C8051F58x |
| Instruction Set Architecture | CISC |
| Device Core | 8051 |
| Core Architecture | 8051 |
| Maximum CPU Frequency (MHz) | 50 |
| Maximum Clock Rate (MHz) | 50 |
| Data Bus Width (bit) | 8 |
| Program Memory Type | Flash |
| Program Memory Size | 128KB |
| RAM Size | 8.25KB |
| Maximum Expanded Memory Size | 64KB |
| Programmability | Yes |
| Interface Type | CAN/I2C/SMBus/SPI/UART |
| Number of I/Os | 25 |
| No. of Timers | 6 |
| Timers Resolution (bit) | 16/16/16/16/16/16 |
| PWM | 4 |
| Number of ADCs | Single |
| ADC Channels | 32 |
| ADC Resolution (bit) | 12 |
| USART | 0 |
| UART | 2 |
| USB | 0 |
| SPI | 1 |
| I2C | 1 |
| I2S | 0 |
| CAN | 1 |
| Ethernet | 0 |
| Watchdog | 1 |
| Analog Comparators | 3 |
| Parallel Master Port | No |
| Real Time Clock | No |
| Special Features | CAN Controller |
| Minimum Operating Supply Voltage (V) | 1.8 |
| Typical Operating Supply Voltage (V) | 2.5|3.3|5 |
| Maximum Operating Supply Voltage (V) | 5.25 |
| Minimum Operating Temperature (°C) | -40 |
| Maximum Operating Temperature (°C) | 125 |
| Supplier Temperature Grade | Automotive |
| Packaging | Tray |
| Mounting | Surface Mount |
| Package Height | 1.4 |
| Package Width | 7 |
| Package Length | 7 |
| PCB changed | 32 |
| Standard Package Name | QFP |
| Supplier Package | PQFP |
| Pin Count | 32 |
| Lead Shape | Gull-wing |
Used in any modern day system or circuit design this C8051F582-IQ microcontroller from Silicon Laboratories, will make any design more versatile. This microcontroller has a minimum operating temperature of -40 °C and a maximum of 125 °C. It has a maximum clock speed of 50 MHz. Its flash program memory is 128KB. This is a 8 bit processor. Its ADC resolution is 12. This device has a typical operating supply voltage of 2.5|3.3|5 V. Its minimum operating supply voltage of 1.8 V, while its maximum is 5.25 V. This device is based on the 8051 core architecture.
