Programmable Devices

Arrow.com offers a wide selection of programmable devices from top industry manufacturers including Intel, Lattice Semiconductor, Microchip, Texas Instruments and Cypress Semiconductor. Shop from thousands of programmable logic devices (PLD), including FPGAs and CPLDs, and find IP cores for a wide variety of embedded systems. We also stock programmable logic dev boards and kits of all types for fast embedded prototyping.

Programmable devices usually refers to chips that incorporate configurable logic circuits. These include Field Programmable Logic Devices (FPGAs), Complex Programmable Logic Devices (CPLD) and Programmable Logic Devices (PLD, PLA, PAL, GAL). There are also devices that are the analog equivalent of these called field programmable analog arrays. These devices invariably have a number of ways to program them, and may contain internal flash to store configuration data. Such programming interfaces include serial and parallel connections to external non-volatile memory, a bus connection to a microcontroller, or JTAG connection directly to a computer for download and debugging in development.

FPGAs contain arrays of configurable logic blocks that are interconnected by configurable switch arrays. They can also incorporate memory, digital signal processing, memory interface, transceiver and clock modules that are configurable, and can be wired to and from the logic blocks. The logic elements (also referred to as logic cells or complex logic blocks) are arrayed in yet larger structures (logic array blocks) to efficiently implement complex logic functions. They have highly flexible I/O banks that can be configured to support different voltages and bus standards. There may also be special hardwired memory controllers or processors available on the die for connection to the logic. CPLDs and PLDs are much simpler versions of FPGAs and typically incorporate non-volatile memory for self-configuration upon power up.

The internal logic and configuration of FPGAs and CPLDs is usually performed at power up by a serial shift register style loading process that sets an invisible layer of configuration registers to set wire muxes and logic connections. This configuration image is compiled by sophisticated software tools that interpret hardware descriptive languages or schematics. Descriptions are analyzed, optimized and synthesized into net lists. The net list is then targeted to the physical resources of the particular device in a mapping, fitting, floor-planning and optimization process so as to meet the timing requirements of the circuit.