Computers, peripherals, phones, clocks, fans, control devices and more — USB is being used for power delivery and connectivity in an ever-expanding range of applications. With the growing complexity of some of these applications, though, it can be tough to integrate USB capability at times. Read this article and learn how to use the Infineon EZ-PD™ PMG1 MCU family in USB power delivery (PD) dual-role power (DRP) applications.
EZ-PD™ PMG1 introduction
Infineon’s EZ-PD™ PMG1 (first-generation PD microcontroller) is a family of high-voltage USB-C PD MCUs. These chips include an Arm® Cortex®-M0/M0+ CPU and USB-C PD controller along with the analog and digital peripherals. EZ-PD™ PMG1 is targeted for any embedded system that provides or consumes power to or from a high-voltage USB-C PD port and leverages the MCU to provide additional control capability. The PMG1 MCU family is fully compliant with the USB PD and Type-C standards. Table 1 compares the features of different MCUs in the EZ-PD™ PMG1 family.
Table 1: Comparison of features of different EZ-PD™ PMG1 family MCUs
| Subsystem or range | Item | PMG1-S0* | PMG1-S1 | PMG1-S2 | PMG1-S3 |
|---|---|---|---|---|---|
| CPU and memory subsystem | Core | Arm® Cortex®-M0 | Arm® Cortex®-M0 | Arm® Cortex®-M0 | Arm® Cortex®-M0+ |
| Maximum frequency (MHz) | 48 | 48 | 48 | 48 | |
| Flash (KB) | 64 | 128 | 128 | 256 | |
| SRAM (KB) | 8 | 12 | 8 | 32 | |
| Power delivery | PD ports | 1 | 1 | 1 | 1 port for 48-QFN 2 ports for 97-BGA |
| Role | Sink | DRP | DRP | DRP | |
| MOSFET gate drivers | 1× PFET | 2× PFET | 2× NFET | Flexible 2× NFET | |
| Fault protections | VBUS OVP and UVP | VBUS OVP, UVP and OCP SCP and RCP (for source configuration only) |
VBUS OVP, UVP and OCP | VBUS OVP, UVP and OCP SCP and RCP (for source configuration only) |
|
| USB | Integrated full-speed USB 2.0 device with billboard class support | No | No | Yes | Yes |
| Voltage range | Supply (V) | VDDD (2.7 to 5.5) VBUS (4 to 21.5) |
VSYS (2.75 to 5.5) VBUS (4 to 21.5) |
VSYS (2.7 to 5.5) VBUS (4 to 21.5) |
VSYS (2.8 to 5.5) VBUS (4 to 28) |
| I/O (V) | 1.71 to 5.5 | 1.71 to 5.5 | 1.71 to 5.5 | 1.71 to 5.5 | |
| SCB (configurable as I2C/UART/SPI) | 2 | 4 | 4 | 7 for 48-QFN (out of which 5 can be configured as SPI and UART) 8 for 97-BGA |
|
| TCPWM block (configurable as timer, counter or pulse width modulator) | 4 | 2 | 4 | 7 for 48-QFN 8 for 97-BGA |
|
| Hardware authentication block (Crypto) | No | No | Yes (AES-128/192/256, SHA1, SHA2-224, SHA2-256, PRNG, CRC) | Yes (AES-128, SHA2-256, TRNG, vector unit) | |
| Analog | ADC | 2× 8-bit SAR | 1× 8-bit SAR | 2× 8-bit SAR | 2× 8-bit SAR 1× 12-bit SAR |
| On-chip temperature sensor | Yes | Yes | Yes | Yes | |
| Direct memory access (DMA) | DMA | No | No | No | Yes |
| GPIO | Maximum number of I/Os | 12 (10+2 OVT) | 17 (15+2 OVT) | 20 (18+2 OVT) | 26 (24+2 OVT) for 48-QFN 50 (48 + 2 OVT) for 97-BGA |
| Charging standard | Charging source | - | BC 1.2, AC | BC 1.2, AC | BC 1.2, AC, AFC, and Quick Charge 3.0 |
| Charging sink | BC 1.2, Apple charging (AC) | BC 1.2, AC | BC 1.2, AC | BC 1.2, AC | |
| ESD protection | ESD protection | Yes (up to ±8 kV contact discharge, up to ±15 kV air discharge, human body model and charged device model) | Yes (human body model and charged device model) | Yes (up to ±8 kV contact discharge, up to ±15 kV air discharge, human body model and charged device model) | Yes (human body model and charged device model) |
| Packages | Package options | 24-QFN (4 × 4 mm, 0.5 mm pitch) | 40-QFN (6 × 6 mm, 0.5 mm pitch) 42-CSP (2.63 × 3.18 mm, 0.4 mm pitch) | 40-QFN (6 × 6 mm, 0.5 mm pitch) | 48-QFN (6 × 6 mm, 0.5 mm pitch) 97-BGA (6 × 6 mm, 0.5 mm and 0.65 mm pitch) |
*PMG1-S0 is a USB PD sink-only device, and therefore does not support DRP applications.
USB PD specifications
This section reviews the basics of USB PD. The USB PD specification defines how a PD-enabled USB Type-C port can get the required power from VBUS by negotiating with a USB PD-compliant power source.
A USB-C port providing power is known as a "source", and a USB-C port consuming power is known as a "sink". There is only one source port and one sink port in each PD connection. In the legacy USB specification, the USB port on the host computer (such as a notebook or a PC) was always a source and the USB peripheral device was always a sink. The USB PD specification allows the source and sink to interchange their roles so that a USB peripheral device (such as an external self-powered hard disk, dock or monitor) can supply power to a USB host. These new power roles are independent of the USB data transfer roles between the USB host and USB device. An example is a self-powered USB peripheral such as a monitor that can charge the battery of a notebook or PC, which is a USB host.
Type-C and USB PD architecture of a DRP port
System policy manager: The PD specification defines a system policy manager that is implemented on the USB host running as an operating system stack. For more details, see the USB PD specification.
Device policy manager: The device policy manager is the module running in the power provider or power consumer, which applies a local policy to each port in the device via the policy engine.
Source port: The source port is the power provider port, which supplies power over VBUS. It is, by default, a USB port on the host or hub.
Sink port: The sink port is the USB power consumer port, which consumes power over VBUS. It is, by default, a USB port on a device.
Policy engine: The policy engine interprets the device policy manager’s input to implement the policy for the port. It also directs the protocol layer to send messages.
Protocol: The protocol layer creates the messages for communication between port partners.
Physical layer: The physical layer sends and receives messages over either VBUS or the configuration channel (CC) between port pairs.
Power source: The ability of a PD port to source power over VBUS. This refers to a Type-C port with Rp asserted on CC.
Power sink: The ability of a PD port to sink power from VBUS. This refers to a Type-C port with Rd asserted on CC.
Cable detection module: The cable detection module detects the presence of an electronically marked cable assembly (EMCA) cable attached to a Type-C port.
Dual-role devices can be developed by combining both provider and consumer elements in a single device.
When a USB host and USB device are interconnected, they form a USB link pair, and each link partner has a CC controller. Messages are then logically exchanged among device policy managers within each PD controller. These messages are physically transferred over the CC, and a PD contract is set up between the link pair, and then the power is delivered over VBUS. The CC is a new signal pair in the Type-C signal definition (see the Type C signal definitions section for more details).
Type-C signal definitions
Figure 2 shows the USB Type-C receptacle, plug and flipped-plug signals. The USB Type-C receptacle has USB 3.1 (TX and RX pairs) and USB 2.0 (Dp and Dn) data buses, USB power (VBUS), ground (GND), CC signals (CC1 and CC2), and two sideband use (SBU) signal pins.
As listed in Table 2 and Table 3, the descriptions of the USB Type-C plug and receptacle signals are the same, except for the CC and VCONN signals. The two sets of USB 2.0 and USB 3.1 signal locations in this layout facilitate the mapping of the USB signals independent of the plug orientation in the receptacle.
Table 2: USB Type-C receptacle signals
| Signal group | Signal | Description |
|---|---|---|
| USB 3.1 | TX1p, TX1n, RX1p, RX1n, TX2p, TX2n, RX2p, RX2n |
The SuperSpeed USB serial data interface defines a differential transmit pair and a differential receive pair. On a USB Type-C receptacle, two pairs of SuperSpeed USB signal pins are defined to enable the plug-flipping feature. |
| USB 2.0 | Dp1, Dn1 Dp2, Dn2 |
The USB 2.0 serial data interface defines a differential pair. On a USB Type-C receptacle, two sets of USB 2.0 signal pins are defined to enable plug flipping. |
| Configuration channel | CC1, CC2 | The CC in the receptacle detects the signal orientation and channel configuration. |
| Auxiliary signals | SBU1, SBU2 | Sideband use. See the USB Type-C Cable and Connector Specification Revision 2.1 for more details. |
| Power | VBUS | USB cable bus power. |
| GND | USB cable return current path. |
Table 3: USB Type-C plug signals
| Signal group | Signal | Description |
|---|---|---|
| USB 3.1 | TX1p, TX1n RX1p, RX1n TX2p, TX2n RX2p, RX2n |
The SuperSpeed USB serial data interface defines a differential transmit pair and a differential receive pair. On a USB Type-C plug, two pairs of SuperSpeed USB signal pins are defined to enable the plug-flipping feature. |
| USB 2.0 | Dp, Dn | On a USB Type-C plug, the USB 2.0 serial data interface defines a differential pair. |
| Configuration channel | CC | The CC in the plug is used for connection detection and interface configuration. |
| Auxiliary signals | SBU1, SBU2 | Sideband use. See the USB Type-C Cable and Connector Specification Revision 2.1 for more details. |
| Power | VBUS | USB cable bus power. |
| VCONN | Type-C cable plug power. | |
| GND | USB cable return current path. |
When a cable with the Type-C plug is inserted into the receptacle, one CC pin is used to establish signal orientation, and the other CC pin is repurposed as VCONN for powering the electronics in the USB Type-C cable (plug).
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