USB Type C Poses New Challenges for Power System Designers

But all is not sweetness and light: as we’ll see, the new specifications raise the bar considerably for the power delivery system.

Brief Summary of the New Standards

What are the main changes in the new standards? Here’s a very short summary.

The last major revision of USB—USB 3.0—raised the data rate of USB 2.0 from 480 Mbps to 4.8 Gbps, improved bus utilization with synchronous operation, and introduced full-duplex operation. In addition, it increased power capability from 500 mA to 900 mA. USB 3.1 builds on USB 3.0, but increases the data rate to 10 Gbps. 

USB Type C is a reversible form factor connector that will replace the current assortment of variously sized Type A and Type B connectors. USB Type C controllers must not only determine the orientation of the connector, they must identify which protocol (USB 2.0, 3.0 or 3.1) is supported by the newly connected device. 

In contrast to the 5 V-only power supply of traditional USB connections, USB PD defines several power profiles that allow devices to request higher currents and supply voltages than they could previously. For example, one profile allows devices to request up to 2 A at 5 V (for a power consumption of up to 10 W); another profile allows a device to request up to 5 A at either 12 V (60 W) or 20 V (100 W).

USB PD uses a single-wire communication protocol that begins after a USB Type C plug insertion is detected. USB PD uses real-time negotiation between systems to determine which device is the provider—the downstream facing port (DFP) in USB PD parlance—and which device is the consumer, or upstream facing port (UFP). The specification allows devices to reverse roles after a further negotiation if conditions should change later.

The DFP and UFP then mutually establish a power delivery scheme or “contract;” this allows both devices to operate at their optimal power levels. Consumers only request the power they need, while providers only grant the power available. 



Figure 1: USB Type C ecosystem. (Source: NXP Semiconductors)

Power Design Issues in Meeting the New Standards

Together, these standards promise to make USB users’ lives a lot easier, while at the same time complicating the lives of power system designers. There are two main issues for power designs transitioning from USB 2.0: 

• At the system level, the new USB specifications require a complete redesign of the old USB 2.0 power management architecture. Not only does the new design have to accommodate USB Type C and its reversible connector, power can flow in either direction, devices can switch function during system operation, and the power levels used are considerably higher: up to 5 A at 20 V (100 W) versus USB 2.0’s 500 mA at 5 V (2.5 W).

• At the circuit level, USB 3.1’s SuperSpeed+ mode, with its 10 Gbps data rate, requires that any additional capacitance be kept to an absolute minimum, which imposes severe restrictions on ESD protection devices. The higher voltage and current also force changes to the protection device specifications.  

System-Level Design Issues

At the system level, the USB PD device is responsible for many more functions than the simple pre-USB PD controller, which simply has to comply with USB power standards by supplying the specified voltage and power.

As mentioned above, a USB PD controller must carry out a complex series of operations. First, it must detect when a cable is plugged into the Type C connector and determine its orientation. Then it negotiates a USB PD power contract with the other device via the CC lines to determine the appropriate functionality and power levels using the USB PD bi-phase marked coding (BMC) and physical layer (PHY) protocol. 

Once negotiations are complete, the controller enables the appropriate power path and configures the USB PD Alternate Mode settings, which allow concurrent use of other protocols such as DisplayPort. At any time during operation, the contract may be renegotiated if conditions change, so the controller must respond to new inputs as appropriate. 

Sample USPD Controllers

This level of functionality demands a complex mixed-signal System-on-Chip (SoC) device, usually including a microcontroller core and an analog ASIC. Typical devices use internal FETs for 5 V and 12 V power delivery and external power FETs if 20 V, 5 A is required.

Texas Instruments’ TPS65982 is a USB Type C and USB PD controller, which includes six major blocks—a cable plug and orientation block; a USB PD PHY; an ARM-core based, fully configurable port policy manager; a power management block; power paths with internal 3 A and optional 20 V/5 A FETs; and an integrated high-speed mix for enhanced Alternate Mode functionality. The TPS65986 is a similar device without the external FET capability. Target applications include notebook computers, tablets and ultrabooks, docking systems, and USB PD-enabled bus-powered devices, as well as other protocols via USB PD Alternate Mode such as DisplayPort, Thunderbolt, and HDMI.    



Figure 2: TPS65982 power interface in a charger application with 20 V capability. (Source: Texas Instruments)

The CCG1 from Cypress Semiconductor incorporates a 48-MHz ARM 32-bit Cortex-M0 Processor with 32 KB Flash and 4 KB SRAM, two configurable 16-bit TCPWM blocks, and a serial communication block (SCB) with I2C (master or slave), SPI (master or slave), or UART capability.  Other features include integrated Type C transceivers, a 12-bit, 1-Msps ADC for VBUS voltage and current monitoring, and up to 30 GPIOs.

NXP Semiconductor also has a portfolio of USB Type C products including a complete USB Type C solution, which features authentication to validate a device and determine whether specific functionality of that device should be enabled. This has a number of benefits including increased battery life and prevention of safety hazards or equipment damage from low-quality materials or non-compliant products. 

Other NXP devices include ARM-based MCUs with USB-PD firmware; signal conditioners to improve transmission distances and reduce bit error rate (BER); and N-channel power switches that automatically isolate a system from a faulty source or load.

ESD Protection for USB 3.1 and USB PD

USB 3.1 uses the same differential signaling lines as USB 3.0, but doubles the data rate to 10 Gbps. As speeds increase, it is vital for the interface to maintain impedance matching throughout the signal path. Any impedance mismatch will cause reflections on the line, which will increase jitter and potentially compromise signal quality, so USB 3.1 systems require stringent capacitance limits for any external components in the signal path. 

Although ESD protection devices do add capacitance, they are a critical component. Migrating to smaller process geometries might result in increased speed, but it also increases susceptibility to ESD pulses. Not only that, a USB port on a consumer device such as a laptop or mobile phone is being used in an uncontrolled ESD environment. Forget about wrist-grounding straps or grounded table surfaces. Instead, consumers are quite likely to accidently touch a connector pin while connecting or disconnecting a plug—right after walking across a nylon carpet or petting the cat!

With traditional device architectures, as ESD protection levels increase, so does device capacitance, forcing designers to choose between signal integrity and ESD protection. Semiconductor diodes have many desirable characteristics, such as low clamping voltages, fast turn-on time, and better reliability, but up until recently have had higher capacitance than other architectures.

Now, though, manufacturers are introducing diode-based protection devices with very low capacitance specifically for high-speed applications. The PUSB3FR4 from NXP Semiconductor, for example, is designed to protect high-speed interfaces such as SuperSpeed USB 3.1 at 10 Gbps. The device includes four high-level ESD protection diode structures and is encapsulated in a leadless small DFN2510A-10 (SOT1176-1) plastic package. All signal lines are protected by a special diode configuration offering ultra-low line capacitance of 0.29 pF. The diodes utilize a snap-back structure in order to provide protection to downstream components from ESD voltages up to ±15 kV contact exceeding IEC 61000-4-2, Level 4. 

The similar PUSB3FR6, with six ESD devices, offers system-level protection for the USB 2.0 and USB 3.1 combination, which is a feature of the USB Type C connector.



Figure 3: ESD7008 clamping response to IEC61000-4-2 +/-8 kV contact ESD pulse. (Source: ON Semiconductor)

ON Semiconductor is also active in this market. Its ESD7008 offers ESD protection for four differential pairs (8 lines) in an UDFN18 package. The flow-through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance. The device features 0.12 pF typical capacitance to ground.

Conclusion

USB Type C, USB 3.1 and USB PD together are the future of USB. The innovative aspects of the complete system—the reversible connector, the increased speed, and the new PD format—certainly pose design challenges for power system designers, but the first solutions have already been introduced, and many others are in the final stages of development.