Altera/Intel Programmable SolutionsEP3SL110F1152I4N现场可编程门阵列
FPGA Stratix® III L Family 107500 Cells 450MHz 65nm Technology 1.1V 1152-Pin FC-FBGA
| Compliant with Exemption | |
| 3A001.a.7.a | |
| LTB | |
| SVHC | Yes |
| SVHC超标 | Yes |
| Stratix® III L | |
| 744 | |
| 65nm | |
| 24 | |
| Utilize Memory | |
| 1.1 | |
| 107500 | |
| 288 (18x18) | |
| SRAM | |
| 4875 | |
| 12+275+2150 | |
| DS1/E1 TDM over Packet IP core|EtherCAT|EtherNET/IP|RapidIO to AXI Bridge Controller (RAB)|Sub-frame Latency JPEG 2000 Encoder (BA130) | |
| Barco Silex/Mobiveil, Inc | |
| 107500 | |
| 16 | |
| 8 | |
| No | |
| No | |
| Yes | |
| No | |
| 450 | |
| 4 | |
| LVDS|LVPECL | |
| LVCMOS|LVTTL | |
| DDR2 SDRAM|DDR3 SDRAM|QDRII+SRAM|RLDRAM II | |
| 1.05 | |
| 1.15 | |
| 1.2|1.5|1.8|2.5|3.3 | |
| -40 | |
| 100 | |
| Industrial | |
| Stratix |
| EDA / CAD Models |