Learn how the MoSys Quad Partition Rate (QPR) device offers increased density and bandwidth with an PCB layout and a lower latency SerDes protocol over current Quad Data Rate (QDR) devices in this article by Mark Baumann, Director of Product Definition and Applications at MoSys, Inc.
The most popular Static device on the market today is a QDR or Quad Data Rate device. It is SRAM that is 144Mb in density (with one option at 288Mb) and uses separate Input and Output bus structures, that run as single ended HSTL bus lines.
For QDR device developers and manufacturers, achieving the desired bandwidth and throughput for most vendors required using separate read and write bus structures. Implementing the two busses requires well over 100 signal pins per device. This, in turn, creates a very challenging task. The user of the QDR device needs to route and maintain trace matching, as well as the signal integrity of single-ended signals at approximately 1GHz. All for just 144Mb of storage.
What MoSys has developed, after reviewing the complexities of the QDR device, was to take a very different approach. The initial goals were:
- • Much larger density than the SRAM device
- • Improve on signal routing
- • Improved signal integrity issues
- • Meet or better the bandwidth that is achievable with a QDR device
Out of this effort, MoSys has developed a QPR (Quad Partition Rate) device. The features of it are:
- • 4x to 8x the density of a QDR
- • Minimum of 2x the bandwidth
- • Using SerDes I/Os for ease of layout (32 pins)
- • A Low Latency SerDes protocol to address the SerDes overhead issue
If the MoSys QPR devices that are presently available are considered, the MSQ220 is 576Mb (or 4 x the 144Mb QDR device) and the MSQ 230 device is 1.1Gb (or 8 x the 144Mb QDR device). This directly addresses the first objective in development of the QPR devices.
The second feature, to attain a minimum of 2x the bandwidth of the present QDR devices, was also achieved. Currently the QRD devices achieve approximately 2B transactions per second. The MSQ220 achieves approximately 4B transactions per second and the MSQ230 achieve approximately 5B transactions per second.
The third objective was to ease the burden of pins on the host device that talks to a memory, and also to ease the routing concerns for a PCB design. This is required to handle routing of high-speed single ended, trace length matched traces. Because the QDR devices are running signals at approximately 800MHz or higher, there are restrictions on how PCB traces can be routed for length, trace-to-trace differences (both length and spacing), PCB layers to run the signals, and length of traces on the board. All these restrictions or requirement place a burden on the insurance of a PDB design. In addition, since the devices require greater than 100 signals per device, it adds the burden of maintaining all the restrictions across a large swath of the board.
When the QPR devices decided to move the I/Os to SerDes, many of these burdens were eased. This is because SerDes I/Os on the QPR devices are capable of auto adaptation. This feature was designed to support driving traces that are up to 10 inches long, which provides more placement freedom and also allows for a lane-to-lane variation in trace routing of a few inches. The I/Os also support re-ordering which allows for the PCB designer to route the interface as cleanly as possible while the device will (internally) automatically re-order the bit ordering on the bus. For example, if it is easiest to hook output X of the host to input Y of the QPR device, it's allowed and the QPR device will internally re-order the inputs to align 0 to 0, 1 to 1 etc. MoSys believes all this flexibility provides a quicker, easier, more reliable PCB routing design in comparison to the burdens seen with wide parallel bus schemes, like those on today’s SRAMS.
Another significant benefit of using SerDes, that addresses the third bullet above, is that for equal or even greater bandwidth where a fraction of the number of pins are needed to transfer the desired data bandwidth. For example, a single QDR device requires greater than 100 pins, with a QPR device with close to 2x the bandwidth only 32 signal pins are required. This is a direct benefit of using differential signaling that can easily run at 4x the signal speed of single ended traces.
However, SerDes are not the perfect answer to interfacing with a memory device. For all of its routing and bandwidth benefits, it does carry with it an overhead of needing a protocol for handling all the link training, link recovery, and error handling that may occur when running links at 10.3125Gbps, 15Gbps or 25Gbps. This is the purpose of developing a protocol, which MoSys has called Giga-Chip Interface (GCI) which addresses issues of latency, protocol overhead and link reliability.
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