Considerations when designing crystals into STM32 microcontrollers

Spec parameters that impact SMT32 MCU crystal oscillator design

1. Start-up - Start-up performance can be looked at in two ways; firstly, if the oscillator will start up consistently in the application under environmental conditions, and secondly how long it takes to start up at power up. The data sheet parameters that affect start-up are CL, ESR, and C0. Making any of these lower improves gain margin that improves start-up. A greater-depth explanation is discussed in Section 5 which covers Gain Margin.

Figure 1 – Oscillator Start-up

Figure 1 shows a typical Vdd rise from 0V and how oscillator closed loop gain increases until unity gain is reached, and the oscillator loop stabilizes, locking onto the resonator frequency. The time from 0V to start-up of stable oscillation is shown a Start-up time.

2. Cost - Mass production volumes impact the global market for all BOM items that make up a crystal resonator. The 3.2 x 1.5 mm size is currently the largest volume seller, so we see prices very competitive in this size. ECS has the largest selection in this size as STM32 Reference Designs, with 20 options. The trend is towards smaller sizes are generally with 2.0 x 1.2 mm the next used option. Cost increases with further package size reduction.

3. Package Size - As mentioned above the trend is for smaller package sizes, as driven by mobile wireless solutions. ECS Inc offers the widest selection of watch crystals in the industry with referenced part numbers for all STM32 MCUs. These range from 1.2 x 1.0 mm to 8.0 x 3.8 mm. Different package sizes offer different constraints, one of the major parameters is the ESR. Due to the crystal blank size, the ESR increases as package size reduces, this, in turn, impacts the gm_crit of the crystal. The ESC Selection Tool helps here, allowing the designer to make these considerations.

4. Tolerance – Most designs will look for a standard 20ppm tolerance crystal; tolerance is the manufacturing measured ppm range at 25°C. In some applications, tighter tolerance is important, and this is again where the ECS selection tool helps to narrow the range of options.

5. Drive Level – Drive level is an important parameter to meet at both ends of the spectrum. Too low and the crystal won’t start up, too high and the crystal could be damaged or the oscillator loop saturate, so that loop gain drops <1 and the oscillator could stop.
1. Low Drive - The ECS Selection Tool lists all parts that have a Gain Margin of 5 or greater for the specific STM32 processor with the selected or standard drive level. This ensures the crystal will start up and is the first priority. The ECS Selection Tool helps the designer to meet this mandatory requirement but then allows you to explore options. Picking a lower gm_crit actual will mean a lower drive current through the crystal, so using less power. ii. High Drive - The other extreme is more drive than the crystal and the oscillator loop can withstand. Some of the STM32 MCUs have a HIGH DRIVE configurable setting, for these, it's recommended to use 12.5pF CL crystal.
2. High Drive - The other extreme is more drive than the crystal and the oscillator loop can withstand. Some of the STM32 MCUs have a HIGH DRIVE configurable setting, for these, it's recommended to use 12.5pF CL crystal.

Figure 2 – Consideration for Drive level STM32 MCU


3. Figure 2 above taken from the STM32 AN2867, shows some of the compromises to consider when using different drive levels. Often low power is the driving factor for handheld or wireless-connected applications. The graph shows selecting 6pF or less CL with medium to low drive levels is a starting point for these applications. The ECS selection Tool helps refine this; by selecting for example F0 Medium Low, the range of CL from 6pF to 4pF can be selected (Ctrl + Select). Then further refinement can be made selecting Size and ESR to find the best solution.
4. Remembering lower CL values result in increased pullability. Therefore, design variances like capacitor tolerance could lead to less accuracy or more variability in production. These lower CL crystals are also more vulnerable to noisy environments. ECS offers some of the lowest ESRs in the industry, if this is a suitable workaround.
5. If low power is not a driving factor, a higher CL value will give more robustness to noisy environments. In these cases where MCU high drive is implemented a 12.5pF CL is advised. This will make the oscillator closed loop less vulnerable to saturation. This saturation situation occurs as the sine wave approaches the supply rails, the amplifier in the closed loop flattens (clips) the sine peaks, suddenly small signal gain instantaneously drops to zero. This only recovers when the output amplitude increases until the nonlinearity reduces the average small signal gain to one, so oscillation can continue. Remember, Barkhausen Criterion, where first condition is that the magnitude of the loop gain (Aβ) must be unity.
6. So overdriving is an issue for the stability of the oscillations and is manifested in no oscillation or high jitter. Equally we need to consider drive through the crystal. The spec will detail the max drive level, and testing should be done to see these criteria are not exceeded.

6. AEC-Q200 options – Automotive grade (AEC-Q200) is another often mandatory option that is required when the designer is making the crystal selection. ECS has a wide range of spec options available in package size 2.0 x 1.2 mm (12Q series) and 3.2 x 15 mm (34Q series). Some of these again can be found using the ECS Selection Tool, but a wider selection is also available in Distribution. If any help is needed to understand the gm_crit of these parts ECS will be pleased to help.

Oscillator loop terminology explained

1. Inv: the internal inverter that works as an amplifier inside the processor
2. XTAL: crystal quartz or a ceramic resonator
3. Rf: internal feedback resistor
4. Rs: external resistor to limit the inverter output current
5. C1 and C2: are the two external load capacitances
6. Cs: stray capacitance, is the sum of the microcontroller pin capacitance (OSC_IN and OSC_OUT) and the PCB (a parasitic) capacitance.
7. gm: Transconductance, where for a small signal is gm = iout / gm_crit
8. Gain Margin or (Safety Factor): gain margin = gm / gmcrit,
9. 9gm_crit max = 4 x ESR x (2πF)² x (C0 + CL)², uses max parameters from crystal data sheet.
10. gm_crit actual = gm_actual = 4 x ESR x (2πF)² x (C0 + CL)², uses actual parameters crystal measurement.

Figure 3 – Shows a typical Pierce Oscillator loop and is common to STM32 MCU LSE crystal oscillators.

Calculating the External Capacitors for LSE oscillator

Figure 3 – Pierce Oscillator Loop showing external capacitors

The external capacitors are an integral part of the design of the oscillator loop. The total capacitance C1 // C2, Cs and Cin and Cout of the MCU all combine to a Total Capacitance. This needs to be the same as the Crystal CL for the frequency to be as near as possible to 32.768KHz.

The following formula describes how to calculate CL: CL = ((Cin + C1) (C2 + Cout) + Cs) / (Cin + C1 + C2 + Cout)

The formula includes the Cin and Cout of the MCU. The Cin is listed in the MCU data sheet, and Cout is normally approximately 2x the Cin.

The lower the crystal CL, the more impact the Cs (Board Strays) has on the capacitor calculation. As mentioned in Section 4e iii, the low CL can be used in low drive applications, but lower CL has more pullability. When using this formula, it shows how the variability of the external capacitors or board stray capacitance will pull the frequency. When considering external capacitors use COG NPO 1% types to minimise the impact of capacitance change over temperature.