When you program a computer in Python, C++, Java, or another high-level language, you have a wide range of functions to help perform the job at hand. The code you write gets interpreted into machine code that your computer or microcontroller uses directly.
Multiple languages ultimately produce machine code that can run on the same type of processor, such as Intel's x86 architecture, so they must agree to a common standard to transform "or" and "print" statements. Instruction Set Architecture (ISA) provides this definition, sometimes referred to as a "contract" between software and hardware.
What is x86 Architecture?
There are many types of processor architectures, as well as many ISAs, which means there are new details to learn and more yak shaving for each one. They can also get bogged down with historical baggage, and the vast majority are closed-source.
One example is the 8086 processor, on which the Intel x86 architecture is based, which was intended as a stopgap when it was released in 1978. Iteration after iteration followed and was built upon through new generations—however, the same basic functionality is still seen in Intel chips today, more than 40 years later. In theory, a modern x86 processor should be able to execute code developed decades ago. Unfortunately, things have changed dramatically, so these additions—expanding from 80 instructions in 1978 to thousands today—mean it isn't nearly as streamlined as it could be.
As noted earlier, the x86 architecture—as well as most computing architecture—is closed-source. If one wants to customize a chip for a specific purpose or analyze the chip's design, that's out of the question, especially at low volumes. This also means that if you're dealing with a complicated system on chip (SoC), there could be several different architectures running inside a single module—inside one chip. These elements all have to play nice together, which creates a potential nuisance for system designers.
What is RISC-V ISA?
You may be led to believe that a plethora of closed ISAs is a necessary evil—and, with a few exceptions, that was the case until 2010. That summer, Andrew Waterman and Yunsup Lee were working on computer architecture research at Berkeley with professors Krste Asanovic and David Patterson.
Not finding a suitable ISA to use, they began developing the RISC-V (Berkley's fifth attempt at a reduced instruction set computer—pronounced "risk five") ISA as a "summer project." This project turned out to be much more than a months-long endeavor. After several years and considerable work, they froze the user spec in 2014, even establishing the RISC-V Foundation to maintain the standard. Today there are more than 250 RISC-V members in 28 countries around the world that support this simplified, open-source, modular ISA. In fact, India has declared it their national instruction set architecture.
Advantages of RISC-V Design
Because RISC-V was designed in 2010, its developers were able to learn from the successes and mistakes of its predecessors, which allowed it to start over with a simplified base ISA known as RV32I. This base will never change, but it can be expanded upon depending on the needs of the application. A small embedded processor might only take advantage of a few of these extensions, while a chip meant for server use can have a wide range of extra capabilities. These capabilities can grow and change over time, but the system at its core will never be universally bloated. Designers can pick, choose, and develop what they need—and only what they need—for their particular uses.
RISC-V Applications: RISC-V ISA Use Cases
Dr. Megan Wachs is VP of Engineering at SiFive, which creates silicon based on this architecture. SiFive created the first commercially available RISC-V chip in 2016 and the first Linux capable multicore chip in 2018. In theory, you could be reading this article right now on a computer running an open-source operating system (Linux) on an open-source processor.
According to Wachs' 2019 Hackaday Superconference talk, RISC-V's goal is "to be the ISA for everything," an architecture that can be used from minuscule embedded processors to server farms, machine learning, and whatever comes next in the decades of computing development. While the ISA is open-source, that doesn't necessarily mean chips designed with it must also be. RISC-V design can be open-source, closed-source, or a mixture of the two.
Widespread RISC-V implementation would eliminate—or significantly reduce—the hassle of setting up and learning to work with different ISAs, and streamlining SoC and other chip designs. Wachs notes that this ISA has grown faster than anyone expected, and it will be interesting to see if the trend continues.
There’s still a long way to go before RISC-V can truly be the ISA for everything, but the potential benefit for system design is significant. The architecture has even been used to create a novel carbon nanotube-based processor that you can read about here.