10 to 160MHz Clock Buffer AN-746 Application Circuit
使用 Analog Devices 的 ADN2812 的参考设计
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依据最终产品
- Automatic Test Equipment
- Instrumentation and Measurement
- Wireless
说明
- AN-746 - ADN2812 is a continuous rate clock recovery, data-retiming device based on a multi-loop PLL architecture. ADN2812 can automatically lock to any data rate from 10 Mbps to 2.7 Gbps, recover clock, and retime data without programming and without need for an external reference clock as an acquisition aid
主要特色
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Operating Frequency10 to 160 MHz
Featured Parts (2)
| 零件编号 | 供应商 | 类别 | 说明 | |||
|---|---|---|---|---|---|---|
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ADN2812ACPZ | Analog Devices | Clock and Data Recovery - CDRs | CDR SONET/SDH 3.3V 32-Pin LFCSP EP Tray | 买入 | |
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ADN2812ACPZ-RL7 | Analog Devices | Clock and Data Recovery - CDRs | CDR SONET/SDH 3.3V 32-Pin LFCSP EP T/R | 买入 | |