I2C Bus Master Reference Design for Lattice CPLD/FPGA devices

使用 Lattice Semiconductor 的 LFE5U-45F-6MG285C 的参考设计

供应商

Lattice Semiconductor
  • 应用类别
    界面
  • 产品类别
    I2C interface

依据最终产品

  • Computers and Peripherals
  • Consumer Electronics
  • Industrial

说明

  • I2C Bus Master Reference Design is intended to demonstrate how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in the CPLD/FPGA device. With the flexibility that this I2C-Bus Master Controller offers, a designer can communicate with up to 128 different I2C slave devices operating in standard or fast mode with transactions ranging from 1 to 256 bytes. The user can also customize the VHDL code to meet their own specific requirements and thus reduce valuable CPLD/FPGA area while maintaining the speed performance. This design conforms to the Philips I2C Bus Specification version 1.0

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