Low Jitter Sampling Clock Generator for High performance ADCs Using the AD9958/AD9858 500 MSPS/1GSPS DDS and AD9515 Clock Distribution IC
使用 Analog Devices 的 AD6645AS 的参考设计
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依据最终产品
- Basestation
- Communications Infrastructure
- Infrared Imaging
- Portable Instrumentation
- Radar System
- Receivers
说明
- Circuit uses a direct digital synthesizer (DDS) with sub-Hertz tuning resolution as a low jitter sampling clock source for high performance ADCs. The AD9515 clock distribution IC provides PECL logic levels to the ADC. The AD9515 internal divider feature also allows the DDS to run at a higher frequency into the AD9515 front end, effectively increasing input slew rate. A higher slew rate into the AD9515 input squaring circuit can help reduce broadband jitter in the clock path
主要特色
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ADC Resolution14 Bit
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ADC Sampling Rate105M SPS
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Number of Channels1CH
Featured Parts (4)
| 零件编号 | 供应商 | 类别 | 说明 | |||
|---|---|---|---|---|---|---|
|
AD9958BCPZ | Analog Devices | Direct Digital Synthesizers - DDS | Direct Digital Synthesizer 500MHz 2-DAC 10bit Serial 56-Pin LFCSP EP Tray | 买入 | |
|
AD9515BCPZ | Analog Devices | Clock Buffers and Drivers | Clock Divider Buffer 2-OUT 1-IN 1:2 32-Pin LFCSP EP Tray | 买入 | |
|
AD6645ASVZ-105 | Analog Devices | Analog to Digital Converters - ADCs | 1-Channel Single ADC Pipelined 105Msps 14-bit Parallel 52-Pin TQFP EP Tray | 买入 | |
|
|
AD6645ASVZ-80 | Analog Devices | Analog to Digital Converters - ADCs | 1-Channel Single ADC Pipelined 80Msps 14-bit Parallel 52-Pin TQFP EP Tray | 买入 | |