Intel FPGAs
| Nº de referencia | Precio | Existencias | Fabricante | Categoría | Family Name | Process Technology | Maximum Number of User I/Os | Number of Registers | Device Logic Cells | Device System Gates | Number of Multipliers | Program Memory Type | RAM Bits - (Kbit) | Total Number of Block RAM | Ethernet MACs | Supported IP Core | Supported IP Core Manufacture | Maximum Number of SERDES Channels | Device Logic Units | Device Number of DLLs/PLLs | Transceiver Blocks | Transceiver Speed - (Gbps) | Dedicated DSP | PCI Blocks | Programmability | Maximum Internal Frequency - (MHz) | Speed Grade | Giga Multiply Accumulates per Second | Differential I/O Standards Supported | Single-Ended I/O Standards Supported | External Memory Interface | Minimum Operating Supply Voltage - (V) | Maximum Operating Supply Voltage - (V) | In-System Programmability | Packaging | Rad Hard | Pin Count | Supplier Package | Standard Package Name | CECC Qualified | ESD Protection | ESCC Qualified | Military | AEC Qualified | AEC Qualified Number | Auto motive | P PAP | ECCN Code | SVHC | SVHC Exceeds Threshold |
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EP2S90F1020C5N
FPGA Stratix® II Family 90960 Cells 609.76MHz 90nm Technology 1.2V 1020-Pin FC-FBGA
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Intel | FPGA | Stratix® II | 90nm | 758 | 90960 | 192 (18x18) | SRAM | 4414.5 | 4+408+488 | 32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz|PowerPC/SH/1960 System Controller|RapidIO to AXI Bridge Controller (RAB)|Viterbi Compiler, High-Speed Parallel Decoder | Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA | 90960 | 12 | 48 | No | 609.76 | 5 | 50.4 | LVDS|LVPECL | CMOS|HSTL|LVTTL|SSTL | DDR SDRAM|DDR2 SDRAM|QDRII+SRAM|RLDRAM II | Yes | 1020 | FC-FBGA | BGA | No | Yes | No | No | No | No | 3A001a.7.a. | Yes | Yes |