TIDEP0033, SPI Master with Signal Path Delay Compensation Reference Design
Diseño de referencia usando la pieza AM4379BZDNA de Texas Instruments
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Documentos asociados
- SPI Master With Signal Path Delay Compensation on PRU-ICSS PCB
- SPI Master With Signal Path Delay Compensation on PRU-ICSS Schematic
- SPI Master With Signal Path Delay Compensation on PRU-ICSS BOM
- SPI Master With Signal Path Delay Compensation on PRU-ICSS Gerber
- SPI Master With Signal Path Delay Compensation on PRU-ICSS CAD Files
Para productos finales
- I/O Sensor Module
- Industrial Communications
- Industrial Gateway - Router
- Industrial Programmable Logic Controllers (PLCs)
- Sensors
Descripción
- TIDEP0033, SPI Master with Signal Path Delay Compensation Reference Design. The Programmable Real-time unit within the Industrial Communication Subsystem (PRU-ICSS) enables customers to support real-time critical applications without using FPGAs, CPLDs or ASICs. This TI design describes the implementation of the SPI master protocol with signal path delay compensation on PRU-ICSS. It supports the 32-bit communication protocol of ADS8688 with a SPI clock frequency of up to 16.7MHz
Características clave
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Embedded System TypeMPU
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Family NameSitara AM437x
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Core ProcessorARM Cortex-A9
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