Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fan-out Buffers
Analog Devices이 부품 ADCLK948 을 사용하는 참조 설계
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최종 제품의 경우
- Test Equipment
- Wireless Infrastructure
- Wireless LAN
Description
- Circuit interfaces ADF4351 integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO) to ADCLK948, which provides up to eight differential, low voltage, positive emitter coupled logic (LVPECL) outputs from one differential output of ADF4351
최종 제품의 경우
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Operating Frequency4500 MHz
피쳐링 부품 (4)
| 부품 번호 | Manufacturer | Type | Description | |||
|---|---|---|---|---|---|---|
|
ADF4351BCPZ | Analog Devices | Clock Generators and Synthesizers | Clock Generator 10MHz to 250MHz-IN 4400MHz-OUT 32-Pin LFCSP EP Tray | 구매 | |
|
|
ADF4351BCPZ-RL7 | Analog Devices | Clock Generators and Synthesizers | Clock Generator 10MHz to 250MHz-IN 4400MHz-OUT 32-Pin LFCSP EP T/R | 구매 | |
|
|
ADCLK948BCPZ | Analog Devices | Clock Buffers and Drivers | Clock Fanout Buffer 8-OUT 2-IN 1:8 32-Pin LFCSP EP Tray | 구매 | |
|
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ADCLK948BCPZ-REEL7 | Analog Devices | Clock Buffers and Drivers | Clock Fanout Buffer 8-OUT 2-IN 1:8 32-Pin LFCSP EP T/R | 구매 | |