Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fan-out Buffers
Reference Design using part ADCLK948 by Analog Devices
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For End Products
- Test Equipment
- Wireless Infrastructure
- Wireless LAN
Description
- Circuit interfaces ADF4351 integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO) to ADCLK948, which provides up to eight differential, low voltage, positive emitter coupled logic (LVPECL) outputs from one differential output of ADF4351
Key Features
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Operating Frequency4500 MHz
Featured Parts (4)
| Part Number | Manufacturer | Type | Description | |||
|---|---|---|---|---|---|---|
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ADF4351BCPZ | Analog Devices | Clock Generators and Synthesizers | Clock Generator 10MHz to 250MHz-IN 4400MHz-OUT 32-Pin LFCSP EP Tray | Buy | |
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ADF4351BCPZ-RL7 | Analog Devices | Clock Generators and Synthesizers | Clock Generator 10MHz to 250MHz-IN 4400MHz-OUT 32-Pin LFCSP EP T/R | Buy | |
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ADCLK948BCPZ | Analog Devices | Clock Buffers and Drivers | Clock Fanout Buffer 8-OUT 2-IN 1:8 32-Pin LFCSP EP Tray | Buy | |
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ADCLK948BCPZ-REEL7 | Analog Devices | Clock Buffers and Drivers | Clock Fanout Buffer 8-OUT 2-IN 1:8 32-Pin LFCSP EP T/R | Buy | |