Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fan-out Buffers
使用 Analog Devices 的 ADCLK948 的参考设计
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依据最终产品
- Test Equipment
- Wireless Infrastructure
- Wireless LAN
说明
- Circuit interfaces ADF4351 integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO) to ADCLK948, which provides up to eight differential, low voltage, positive emitter coupled logic (LVPECL) outputs from one differential output of ADF4351
主要特色
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Operating Frequency4500 MHz
Featured Parts (4)
| 零件编号 | 供应商 | 类别 | 说明 | |||
|---|---|---|---|---|---|---|
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ADF4351BCPZ | Analog Devices | Clock Generators and Synthesizers | Clock Generator 10MHz to 250MHz-IN 4400MHz-OUT 32-Pin LFCSP EP Tray | 买入 | |
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ADF4351BCPZ-RL7 | Analog Devices | Clock Generators and Synthesizers | Clock Generator 10MHz to 250MHz-IN 4400MHz-OUT 32-Pin LFCSP EP T/R | 买入 | |
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ADCLK948BCPZ | Analog Devices | Clock Buffers and Drivers | Clock Fanout Buffer 8-OUT 2-IN 1:8 32-Pin LFCSP EP Tray | 买入 | |
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ADCLK948BCPZ-REEL7 | Analog Devices | Clock Buffers and Drivers | Clock Fanout Buffer 8-OUT 2-IN 1:8 32-Pin LFCSP EP T/R | 买入 | |