Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fan-out Buffers
Analog Devices の部品 ADCLK948 を使用したリファレンス デザイン
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最終製品向け
- Test Equipment
- Wireless Infrastructure
- Wireless LAN
説明
- Circuit interfaces ADF4351 integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO) to ADCLK948, which provides up to eight differential, low voltage, positive emitter coupled logic (LVPECL) outputs from one differential output of ADF4351
主な特徴
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Operating Frequency4500 MHz
注目のパーツ (4)
| 部品番号 | メーカー | タイプ | 説明 | |||
|---|---|---|---|---|---|---|
|
ADF4351BCPZ | Analog Devices | Clock Generators and Synthesizers | Clock Generator 10MHz to 250MHz-IN 4400MHz-OUT 32-Pin LFCSP EP Tray | 買う | |
|
|
ADF4351BCPZ-RL7 | Analog Devices | Clock Generators and Synthesizers | Clock Generator 10MHz to 250MHz-IN 4400MHz-OUT 32-Pin LFCSP EP T/R | 買う | |
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|
ADCLK948BCPZ | Analog Devices | Clock Buffers and Drivers | Clock Fanout Buffer 8-OUT 2-IN 1:8 32-Pin LFCSP EP Tray | 買う | |
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ADCLK948BCPZ-REEL7 | Analog Devices | Clock Buffers and Drivers | Clock Fanout Buffer 8-OUT 2-IN 1:8 32-Pin LFCSP EP T/R | 買う | |