As applications across the commercial, industrial, and defense fields call for feature rich system solutions, the demand for low-power, high-performance FPGAs has exploded. Microsemi has set themselves apart in this fast moving field with the SmartFusion2 and IGLOO2 FPGA families. These low density FPGAs not only provide engineers more resources with lower power, they also come with some of the best debug tools on the market, address increasingly critical security concerns, and provide exceptional reliability.
Quality FPGAs are anchored by the resources they offer. The SmartFusion2 and IGLOO2 FPGA families offer up to 16 lanes of multi-protocol 5G SERDES—more than any competing low density FPGA. They can employ from 5k to 150k LEs for maximum processing performance and versatility. Individually they bring even more specialized support.
The heart of the SmartFusion2 is its 166MHz ARM® Cortex-M3 processor, which is the premier ARM® processor for embedded solutions. It’s based on a 3-stage pipeline Harvard bus architecture that delivers stellar 32-bit performance. Engineers can also take advantage of extensive peripherals and the benefits of the proven ARM® ecosystem. The SmartFusion2 implementation adds Embedded Trace Macrocell (ETM) support and an 8KB instruction cache and comes with embedded SRAM and up to 512Kb eNVM.
The IGLOO2 also offers 2x32 KB eSRAM and up to 512KB embedded flash, and it brings a high-performance memory subsystem of its own—something no other SoC FPGA has. The IGLOO2 FPGA’s High Performance Memory Subsystem has best in class hard IP that includes an embedded DDR3 controller, large SRAM blocks and secure Flash. The FPGA fabric also has two sizes of embedded memory blocks, 18K bits and 1K bits, and these scale with the density of the parts.
Both FPGA families excel when paired with Microsemi’s Libero SoC design suite. Libero SoC is a comprehensive, easy-to-learn development tool that integrates industry standard Synopsys Synplify Pro® synthesis and Mentor Graphics ModelSim® simulation with top of the line constraints management and support. The Libero SoC design suite is tailor made for SmartFusion2 and IGLOO2 families and built for quick and comprehensive development and debug.
Debug has historically been a development time suck, but the SmartDebug tool built in to the Libero SoC design suite coupled with the hardware allows the equivalent of an oscilloscope inside Microsemi’s FPGAs. SmartDebug gives engineers access to any logic element (LE) so that they can check the state of inputs and outputs in real time without re-routing the design. Among the debug methods is Live Probe, in which two probes can be configured to observe any LE, and connect those signals through two dedicated pins to an oscilloscope without recompiling. Another is Active Probe, which can read or write signals on any number of internal nodes and allows users to quickly observe the output of the logic without recompiling. SmartDebug is the only debug tool with this built in oscilloscope capability, made possible by unique architectural features and the Live Probe and Active Probe software tools.
As impressive as these resources are, what makes the most impact in terms of application is that the SmartFusion2 and IGLOO2 families implement designs with the lowest power on the market. Because of significant reductions in static power and SERDES power, their overall design allows for up to 50% power reduction compared to competing FPGAs. Just 70mW per 5G SERDES lane. When not in operation, the SmartFusion2 can go into an ultralow power FlashFreeze mode that consumes a miniscule 7mW standby. This is made all the more impressive considering that these devices have 209 to 574 I/Os depending on the package.
Cutting-edge FPGAs need more than high-performance and low power. Increasingly, these solutions are being used in mission critical and safety critical applications that demand high security as well. The SmartFusion2 and IGLOO2 devices incorporate Microsemi’s layered security approach—three types of security to meet the most stringent demands. Built in IP security prevents reverse engineering or tampering. End to end manufacturing flow means that Microsemi secures your entire design from a hardware level to prevent overbuilding and cloning. The third level is data security. Microsemi FPGAs have built in security blocks that secure incoming and outgoing communications. These solutions are also the only FPGAs with licensed DPA countermeasure protection. Engineers can rest assured that their applications are covered.
Reliability goes hand in hand with safety. Microsemi built the SmartFusion2 and IGLOO2 devices with error free SEU immune fabric configuration. The Flash based FPGAs from Microsemi are the only FPGAs which are SEU error free. Other competitors offer flash on the side FPGAs. These load from a flash block into a SRAM at power up. Since these devices actually run out of SRAM, they are susceptible to SEU errors. For Microsemi’s flash based FPGAs, all SoC memory is SEU protected, including SEU tolerant eSRAM and DDR bridges, and built-in error detection and correction adds a further layer of design confidence. These devices are already deployed in safety critical and mission critical systems including turbines, mass transit, and industrial automation.
No matter what your design is, Microsemi’s low-density IGLOO2 and SmartFusion2 FPGA families can implement a wide variety of functions that excel in I/O expansion and conversion, system management, video and imaging, secure connectivity, PCIe Gen2 interfaces and more. They stand apart from other FPGAs by offering more resources with lower power than any other similar solution on the market, and they are secure and reliable enough for even the most demanding safety critical and mission critical systems.