Interfacing field programmable gate arrays (FPGAs) to an analog-to-digital converter (ADC) output is a common engineering challenge. This article includes an overview of various interface protocols and standards as well as application tips and techniques for utilizing low voltage differential signaling (LVDS) in high speed data converter implementations.
The task is complicated by the fact that ADCs use a variety of digital data styles and standards. Single data rate (SDR) CMOS is very common for lower speed data interfaces, typically under 200 MHz. In this case, data is transitioned on one edge of the clock by the transmitter and received by the receiver on the other clock edge. This ensures the data has plenty of time to settle before being sampled by the receiver. In double data rate (DDR) CMOS, the transmitter transitions data on every clock edge. This allows for twice as much data to be transferred in the same amount of time as SDR; however, the timing for proper sampling by the receiver is more complicated.
This article from Analog Devices discusses the standard interfaces—SPI, I 2 C, SPORT, LVDS and JESD204A—used to connect an FPGA to an ADC and how interfacing FPGAs to ADCs will continue to be a challenge as the data rate further increases with new, faster protocols..