Simple Sigma-Delta Analog-to-Digital Converter in FPGA Reference Design

Description

• Simple Sigma-Delta ADC in FPGA Reference Design. The Simple Sigma-Delta Analog-to-Digital Converter Reference Design targets the implementation of an analog-to-digital converter in a Lattice CPLD or FPGA. This reference design supports the use of an external analog comparator device, or optionally an on-chip LVDS buffer in devices with differential LVDS input support. Implementing this reference design can eliminate the need for dedicated and expensive analog-to-digital circuits (ADC), power supply monitors and/or transducers. The design can be implemented with few logic resources and is flexible enough to meet a variety of applications. The Simple Sigma-Delta ADC is an excellent choice for monitoring various sensors and power rails of a system