Power Management Bus (PMBus) based on the Lattice reference design RD1046 I2C Master with WISHBONE Bus Interface
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- Power Management
Description
- Power Management Bus (PMBus) Reference Design is an open standard protocol that was defined as a means to communicate with power conversion and other devices. As an industry standard serial communication interface based on SMBUs protocols, it is viewed as an extension of the System Management Bus and supports many new functions. Like SMBus, the PMBUs protocol defines three layers, the Physical Layer, the Data Link Layer and the Network Layer. This design contains a WISHBONE interface and focuses on the implementation of the Data Link Layer protocol. It is convenient to connect this design with a microcontroller which implements the Network Layer protocol. This design is based on a reference design RD1046: I2C Master with WISHBONE Bus Interface
Pièces en vedette (2)
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LCMXO2-2000HC-4TG100C2U | Lattice Semiconductor | Complex Programmable Logic Devices - CPLDs | FPGA MachXO2 Family 2112 Cells 65nm Technology 2.5V/3.3V 100-Pin TQFP Tray | Ajouter au panier | |
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LCMXO2-2000HC-4TG100C | Lattice Semiconductor | Complex Programmable Logic Devices - CPLDs | FPGA MachXO2 Family 2112 Cells 65nm Technology 2.5V/3.3V 100-Pin TQFP Tray | Ajouter au panier | |